As time goes on, semiconductor devices continue to shrink in size and grow in density and complexity. This has driven a migration towards a "System on a Chip" where different devices are built in to a single computer chip. For example, logic structure and memory structures may be included in one chip. Along these lines, one chip could include logic, DRAM, SRAM, NVRAM and/or SiGe features.
As the complexity in manufacturing these semiconductor chips increases, there is often a need to optimize conflicting needs from different devices. For example, while logic portions of a chip may require changing channel length to tradeoff speed against yield, this variability in channel length may have a negative impact on the storage parts of chips.
Also, many semiconductor devices are very sensitive to feature size differences across a chip or wafer. As feature sizes continue to decrease and the number of features on a single chip increases, line width uniformity specifications become tighter with each generation. A variety of methods may be employed to improve uniformity and decrease line width variation.